Non-volatile memory devices are well known in the art. For example, a split-gate memory cell is disclosed in U.S. Pat. No. 5,029,130. This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions. Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region to determine the programming state of the floating gate).
The configuration and number of gates in non-volatile memory cells can vary. For example, U.S. Pat. No. 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region. U.S. Pat. No. 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate.
FIG. 1 illustrates a split gate memory cell 10 with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12. A channel region 18 of the substrate is defined between the source/drain regions 14/16. A floating gate 20 is disposed over and insulated from a first portion of the channel region 18 (and partially over and insulated from the source region 14). A control gate (also referred to as a word line gate or select gate) 22 has a lower portion disposed over and insulated from a second portion of the channel region 18, and an upper portion that extends up and over the floating gate 20 (i.e., the control gate 22 wraps around an upper edge of the floating gate 20).
Memory cell 10 can be erased by placing a high positive voltage on the control gate 22, and a reference potential on the source and drain regions 14/16. The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism (leaving the floating gate 20 positively charged or more positively charged—the erased state). Memory cell 10 can be programmed by applying a ground potential to drain region 16, a positive voltage on source region 14, and a positive voltage on the control gate 22. Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected (by hot electron injection) onto the floating gate 20 (leaving the floating gate negatively charged or more negatively charged—the programmed state). Memory cell 10 can be read by placing ground potential on the drain region 16, a positive voltage on the source region 14 and a positive voltage on the control gate 22 (turning on the channel region portion under the control gate 22). If the floating gate is positively charged (erased), electrical current will flow from source region 14 to drain region 16 (i.e. the memory cell 10 is sensed to be in its erased “1” state based on sensed current flow). If the floating gate 20 is negatively charged (programmed), the channel region under the floating gate is weakly turned on or turned off, thereby reducing or preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed “0” state based on sensed low or no current flow).
FIG. 2 illustrates an alternate split gate memory cell 24 with same elements as memory cell 10, but additionally with a program/erase (PE) gate 26 disposed over and insulated from the source region 14 (i.e. this is a three gate design). Memory cell 24 can be erased by placing a high voltage on the PE gate 26 to induce tunneling of electrons from the floating gate 20 to the PE gate 26. Memory cell 24 can be programmed by placing positive voltages on the control gate 22, PE gate 26 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20. Memory cell 24 can be read by placing positive voltages on the control gate 22 and drain region 16, and sensing current flow.
FIG. 3 illustrates an alternate split gate memory cell 28 with same elements as memory cell 10, but additionally with an erase gate 30 disposed over and insulated from the source region 14, and a coupling gate 32 over and insulated from the floating gate 20. Memory cell 28 can be erased by placing a high voltage on the erase gate 30 and optionally a negative voltage on the coupling gate 32 to induce tunneling of electrons from the floating gate 20 to the erase gate 30. Memory cell 28 can be programmed by placing positive voltages on the control gate 22, erase gate 30, coupling gate 32 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20. Memory cell 28 can be read by placing positive voltages on the control gate 22 and drain region 16 (and optionally on the erase gate 30 and/or the coupling gate 32), and sensing current flow.
For all the above referenced memory cells, they are typically operated in a digital manner, meaning that voltages are applied in each of the program, erase and read operations to program the memory cells to a “0” state, erase the memory cells to a “1” state, and to read the memory cells to determine whether they are in the programmed state or the erased state. In digital operations, each memory cell can only store one bit of data (i.e., the cell has only two possible programming states), which are read by placing the memory cell above its read threshold whereby it will conduct the read current if not programmed with electrons, and it will not conduct (or conduct very little) if programmed with electrons.
It is also possible to operate the above described memory cells in an analog manner, whereby each memory cell can be programmed to one of many programming states, which is determined by reading the memory cell using a subthreshold read operation. Specifically, each memory cell can be gradually programmed with electrons until a desired programming state is achieved. During a read operation, the memory cell read voltage(s) are selected to place the memory cell in a sub-threshold state (i.e., the read voltage(s) are insufficient to turn the memory cell on no matter its programmed state), so that any current through the channel region of the memory cell represents sub-threshold leakage current. However, that subthreshold leakage current will be proportional to the programming state of the memory cell, and therefore indicative of the programming state of the memory cell. Therefore, in this manner, the memory cells can be used in an analog manner whereby they are programmed to an analog programming state and produce an analog read current that is proportional to the analog programming state. Analog operation is ideal for applications such as neural nets, where the memory cells are used to store individual weight values, and the array is used to perform vector/matrix multiplication (i.e., the neuron layer inputs are placed on the word lines, and are effectively multiplied by the weights stored in the individual memory cells to produce the outputs on the bit lines).
In digital operation, an entire row of memory cells is usually read in a single read operation. This means that not only is the word line activated to its read voltage, but each of the bit lines for that row of memory cells are activated too during the read operation. The peak current demand for digital operation is therefore dictated by the electrical current requirements needed to activate the one word line and all the bit lines. In analog operation, however, all of the word lines and bit lines could be activated simultaneously (e.g., during a vector/matrix multiplication operation). This means that the peak current demand by the memory array in analog operation could be many times that of digital operation. High peak current demand can result in excessive power supply noise which can cause device malfunction, a significant voltage drop which also can cause device malfunction, and detrimental effects for devices powered by RF energy. Sources of the current demand include large word line drivers, bit-line pre-charging, differential op-amps for differential current sensing, and activation. In all cases, voltage and current supplies need to handle the peak voltage and current requirements for operating the memory array, making these devices larger and consume more power.
There is a need for a non-volatile memory array architecture and design that reduces peak power demand and noise.